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Standard features of the I²C bus include the ability to detect data collision
between multiple communicating devices, different modes of operation for
reading and writing at speeds ranging from 100 kbps to 3.4 mbps, and physically
defined bus addresses that can be software defined and allow for easy removal
and addition of devices to the bus during system operation.
The SDA line is a bi-directional serial data line that facilitates data transfer
between master and slave devices, synchronized by the SCL line driven by the
master device. These lines are either open-collector or open-drain, depending on
the type of transistor technology used by the device manufacturer. As seen in
Figure 3.2.1-2, the lines are in an unknown state when not being used, so they
must be set to a known state using a 5V voltage source with current-limiting pull-
up resistors. This sets the condition that both lines are held to a digital logic high
when not in use. The upper limit on the number of devices that can be connected
to a single bus is a function of the bus capacitance, defined by NXP to be no
more than 400pF. Because our system design only incorporates three devices
into the bus, there should be no immediate concern about reaching this upper
limit. With the addition of multiple devices, it would be necessary to calculate the
input capacitance of each device and verify that our design falls within the
standard.
Figure 3.2.1-2 The I²C Bus w/ multiple devices, reprinted with permission from
NXP Semiconductor
In the I²C bus topology, a “Master” is the device that provides the clock source on
the SCL line for the “Slave” devices. In Figure 3.2.1-3, the master device initiates
data communications with a “START” condition, consisting of a HIGH to LOW
transition of the SDA line while the SCL line is at a logical high. The master
device terminates with a “STOP” condition, which consists of a LOW to HIGH
transition of the SDA line while the SCL line is at a logical high. The slave device
can receive and transmit data to the master device, but cannot initiate such
conditions. It is also possible to have multiple master devices on the same I²C
bus, using a method of arbitration to prevent multiple masters from initiating
- Senior Design Group 8 1
- May 3, 2010 1
- TABLE OF CONTENTS 2
- 1. Introduction 4
- 1.2 Motivation 5
- 1.3 Goals and Objectives 6
- 1.5 System Overview 12
- 2. Research and Requirements 13
- 2.2 System Logic 15
- 2.2.3 Microcontroller 20
- 2.3 Voltage Regulator 23
- 2.3.1 Requirements 24
- 2.4.1 USB 31
- 2.4.2 Serial (RS232) 32
- 2.4.3 Non-Standard Connector 33
- 2.4.4 RJ-45 (Out of Spec) 34
- 2.4.5 USB (Out of Spec) 35
- 2.4.6 Wireless 36
- 2.5 LEDs 37
- 2.6 Software 40
- 2.7 Interlock Device 44
- 2.8 Enclosure 45
- Control Box Enclosure 46
- Hand-held Unit Enclosure 49
- 2.9 Display 51
- 2.9.2 Dot-Matrix Display 52
- 2.9.3 Liquid Crystal Display 53
- 2.10 Alcohol Sensor 54
- Fuel Cell Sensors 57
- 2.11 Battery 59
- 2.11.1 Alkaline Battery 60
- 2.11.4 Lithium Ion Battery 63
- 2.11.5 Lead Acid Battery 64
- 2.11.6 Zinc Nickel Battery 66
- 2.11.7 Battery Comparison 66
- 2.12 Charging Circuit 67
- Colin Mitchell of 70
- 2.13 Airflow Measurement 74
- 2.13.2 Pitot Tube 75
- 3. Hardware Design 77
- 3.2.2 Wireless 83
- 3.2.3 Programming 83
- 3.2.4 Analog Sensing 85
- 3.3 Power Supply 86
- 3.4 Display 91
- 3.6.1 Breadboard 93
- 3.6.2 Perforated Board 93
- 3.6.3 Printed Circuit Board 93
- 3.8 Enclosure 97
- Figure 3.8-1 Voog Concept I 98
- Figure 3.8-2 Voog Concept II 99
- 4. Software Design 103
- 4.2 Communications 106
- 4.3 Portable Unit Software 109
- 4.3.1 Display Functions 110
- 4.4 Control Unit Software 111
- 5. Testing and Validation 114
- 5.1.3 Enclosure 115
- 5.1.4 Display 115
- 5.1.2 Gas Detection Sensor 115
- 5.2 Hardware Test Procedure 116
- 5.2.3 Verifying Enclosure 119
- 5.2.4 Verifying Display 119
- 5.3.1 Hand Held Software 122
- 5.3.2 Control Box Software 122
- 5.4 Software Test Procedure 123
- 5.5 System Test Procedure 124
- 6. Administrative Materials 129
- 6.2 Project Planning 130
- 6.2.2 Spring 2010 Semester 131
- 6.3 Cost Estimates 132
- 6.4 Bill of Materials 133
- 6.5 Design Team 136
- Appendix A 137
- A.2 Permissions 138
- A.2.3 Talkingelectronics.com 139
- A.2.4 Greenbatteries.com 140
- A.2.5 Batteryspace.com 140
- A.2.6 Sparkfun.com 141
- A.2.7 reuk.co.uk 142
- Thanks 143
- A.2.12 SI Micro 144
- A.2.13 Newhaven Display 145
- A.2.14 Matrix Orbital 146
- A.2.15 Phidgets 147
- A.2.15 Binder USA 147
- A.2.16 ST Micro 148
Allied Telesis AT-FS724L manuali
Manuali dei proprietari e guide per l'utente per Hardware del computer Allied Telesis AT-FS724L.
We fornisce 2 manuali pdf Allied Telesis AT-FS724L per scaricare gratuitamente in base al tipo di documento: Manuale Utente
Allied telesis AT-FS724L Manuale Utente (41 pagine)
Marchio: Allied-telesis | Categoria: Computer hardware | Dimensione: 0.83 MB |
Indice
Contents
5
Overview
11
Key Features
12
Standards
12
Duplex Mode
14
MAC Address
17
Store and
18
Flow Control
18
Topology
21
Installation
22
13579111315
29
Por t Unm
35
100-240VAC~
37
Allied telesis AT-FS724L Manuale Utente (46 pagine)
Marchio: Allied-telesis | Categoria: Computer hardware | Dimensione: 0.50 MB |
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